SETHULEKSHMI R

Designation: Asst. Professor

Qualification: M.Tech, Pursuing Ph D

Email-id: [email protected]

Experience: 11.5  Yrs

Sl.No
Title of Paper/Journal/ Conference Date
1.     A technical paper on “Verification of a RISC processor IP core using system Verilog”  was presented  in WiSPNET 2016 (IEEE). 2016
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